Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

Conj

Performs element by element conjugation of the vector.

Syntax

IppStatus ippsConj_32fc_A24 (const Ipp32fc*
pSrc
, Ipp32fc*
pDst
, Ipp32s
len
);
IppStatus ippsConj_64fc_A53 (const Ipp64fc*
pSrc
, Ipp64fc*
pDst
, Ipp32s
len
);
Include Files
ippvm.h
Domain Dependencies
Headers:
ippcore.h
Libraries:
ippcore.lib
Parameters
pSrc
Pointer to the source vector.
pDst
Pointer to the destination vector.
len
Number of elements in the vectors.
Description
This function performs element by element conjugation of the vector
pSrc
and stores the result in the corresponding element of the vector
pDst
.
For single precision data:
function flavor
ippsConj_32fc_A24
guarantees 24 correctly rounded bits of significand, including the implied bit, with the maximum guaranteed error within 1 ulp.
For double precision data:
function flavor
ippsConj_64fc_A53
guarantees 53 correctly rounded bits of significand, including the implied bit, with the maximum guaranteed error within 1 ulp.
The computation is performed as follows:
pDst
[n] = CONJ(
pSrc
[n]
),
0 ≤ n <
len
.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when
pSrc1
,
pSrc2
or
pDst
pointer is
NULL
.
ippStsSizeErr
Indicates an error when
len
is less than or equal to 0.

Example

The example below shows how to use the function
ippsConj
.
IppStatus ippsConj_32fc_A24_sample(void)
{
const Ipp32fc x[2] = {{+2.885,-1.809}, {-0.543,-2.809}};
Ipp32fc y[2];
IppStatus st = ippsConj_32fc_A24( x, y, 2 );
printf(" ippsConj_32fc_A24:\n");
printf(" x = %+.3f%+.3f*i %+.3f%+.3f*i \n", x[0].re, x[0].im, x[1].re, x[1].im);
printf(" y = %+.3f%+.3f*i %+.3f%+.3f*i \n", y[0].re, y[0].im, y[1].re, y[1].im);
return st;
}
Output results:
ippsConj_32fc_A24:
x = +2.885-1.809*i -0.543-2.809*i
y = +2.885+1.809*i -0.543+2.809*i

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804