Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

Cosh

Computes hyperbolic cosine of each vector element.

Syntax

IppStatus ippsCosh_32f_A11 (const Ipp32f*
pSrc
, Ipp32f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_32f_A21 (const Ipp32f*
pSrc
, Ipp32f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_32f_A24 (const Ipp32f*
pSrc
, Ipp32f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64f_A26 (const Ipp64f*
pSrc
, Ipp64f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64f_A50 (const Ipp64f*
pSrc
, Ipp64f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64f_A53 (const Ipp64f*
pSrc
, Ipp64f*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_32fc_A11 (const Ipp32fc*
pSrc
, Ipp32fc*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_32fc_A21 (const Ipp32fc*
pSrc
, Ipp32fc*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_32fc_A24 (const Ipp32fc*
pSrc
, Ipp32fc*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64fc_A26 (const Ipp64fc*
pSrc
, Ipp64fc*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64fc_A50 (const Ipp64fc*
pSrc
, Ipp64fc*
pDst
, Ipp32s
len
);
IppStatus ippsCosh_64fc_A53 (const Ipp64fc*
pSrc
, Ipp64fc*
pDst
, Ipp32s
len
);
Include Files
ippvm.h
Domain Dependencies
Headers:
ippcore.h
Libraries:
ippcore.lib
Parameters
pSrc
Pointer to the source vector.
pDst
Pointer to the destination vector.
len
Number of elements in the vectors.
Description
This function computes the hyperbolic cosine of each element of
pSrc
, and stores the result in the corresponding element of
pDst
.
For single precision data:
function flavors
ippsCosh_32f_A11
and
ippsCosh_32cf_A11
guarantee 11 correctly rounded bits of significand, or at least 3 exact decimal digits;
function flavors
ippsCosh_32f_A21
and
ippsCosh_32fc_A21
guarantee 21 correctly rounded bits of significand, or 4 ulps, or about 6 exact decimal digits;
function flavors
ippsCosh_32f_A24
and
ippsCosh_32fc_A24
guarantee 24 correctly rounded bits of significand, including the implied bit, with the maximum guaranteed error within 1 ulp.
For double precision data:
function flavors
ippsCosh_64f_A26
and
ippsCosh_64fc_A26
guarantee 26 correctly rounded bits of significand, or 6.7E+7 ulps, or approximately 8 exact decimal digits;
function flavors
ippsCosh_64f_A50
and
ippsCosh_64fc_A50
guarantee 50 correctly rounded bits of significand, or 4 ulps, or approximately 15 exact decimal digits;
function flavors
ippsCosh_64f_A53
and
ippsCosh_64fc_A53
guarantee 53 correctly rounded bits of significand, including the implied bit, with the maximum guaranteed error within 1 ulp.
The computation is performed as follows:
pDst
[n] = cosh(
pSrc
[n])
,
0 ≤ n <
len
.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when
pSrc
or
pDst
pointer is
NULL
.
ippStsSizeErr
Indicates an error when
len
is less than or equal to 0.
IppStsOverflow
In real functions, indicates a warning that the function overflows, that is, at least one of elements of
pSrc
has the absolute value greater than
Ln(FPMAX) + Ln(2)
, where
FPMAX
is the maximum representable floating-point number.

Example

The example below shows how to use the function
ippsCosh
.
IppStatus ippsCosh_32f_A21_sample(void)
{
const Ipp32f x[4] = {-4.676, -4.054, 6.803, -9.525};
Ipp32f y[4];
IppStatus st = ippsCosh_32f_A21( x, y, 4 );
printf(" ippsCosh_32f_A21:\n");
printf(" x = %.3f %.3f %.3f %.3f \n", x[0], x[1], x[2], x[3]);
printf(" y = %.3f %.3f %.3f %.3f \n", y[0], y[1], y[2], y[3]);
return st;
}
Output results:
ippsCosh_32f_A21:
x = -4.676 -4.054 6.803 -9.525
y = 53.661 28.833 450.219 6849.870

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804