## Developer Reference

• 2020
• 07/15/2020
• Public Content
Contents

# MimoMMSE

DEPRECATED. Implements the MIMO MMSE estimator algorithm.

## Syntax

Include Files
ippe.h
Parameters
pSrcH
Pointer to line 2 of the H matrix.
srcHStride2
Stride between H matrices (H[symb0] and (H[symb1]).
srcHStride1
Stride between rows of the H matrix (h00 and h10)
srcHStride0
Stride between elements of the row (h00 and h01).
pSrcY
Array of pointers to the RX signal Y. The maximum size is four TX antennas and 12 symbols.
Sigma2
Noise power.
numSymb
Number of symbols.
numSC
Number of subcarriers.
pDstX
Pointer to the estimated TX signal grouped by four symbols (quads).
dstXStride1
Stride between TX signals (X[ant0] and X[ant1]).
dstXStride0
Stride between quads inside one antenna.
SINRIdx
Index of symbol to calculate the SINR.
pDstSINR
Pointer to an array of SINR for layer 1,2.
scaleFactor
Scale factor, refer to Integer Scaling.
Description
This function is deprecated and will be removed in a future release. If you have concerns, open a ticket and provide feedback at https://supporttickets.intel.com/.
This functionality is available only within the Intel® System Studio suite.
This function implements the MMSE estimator algorithm. The MMSE estimation process consists of the following steps:
1. Calculate
B
=H
H
*H, where H is the channel matrix, and superscript
H
denotes Hermitian operator (transpose and conjugate).
2. Calculate
A
=H
H
*H+
σ
2
n
*
I
Nt
, where
N
t
is the number of transmit antennas (1 or 2).
3. Calculate
A
-1
=(H
H
*H+
σ
2
n
*
I
Nt
)
-1
.
4. Calculate
Z
=H
H
*
y
.
5. Calculate
x
=
A
-1
*
Z
=(H
H
*H+
σ
2
n
*
I
Nt
)
-1
*H
H
*
y
.
6. Calculate
D
=
W
*H=
A
-1
*H
H
*H.
Signal to interference plus noise ratio (SINR) is computed as follows:
where
M
is the number of subcarriers.
The destination data is grouped by four symbols.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error if one of the specified pointers is NULL.
ippStsSizeErr
Indicates an error if
numSymb
or
numSC
is less than, or equal to zero.

#### Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804