Intel® Integrated Performance Primitives Developer Reference

Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

GetCacheParams

Retrieves cache type, level, and size.

Syntax

IppStatus ippGetCacheParams(IppCache**
ppCacheInfo
);
Include Files
ippcore.h
Parameters
ppCacheInfo
Pointer to an array of structures describing CPU cache, which are defined in
ipptypes.h
:
typedef struct {
int type;
int level;
int size
} IppCache;
where
  • type
     can have the following values:
    0
    NULL
     - no more caches
    1
    Data cache
    2
    Instruction cache
    3
    Unified cache
  • level
     starts with 1
  • size
     is in bytes
Description
The
ippGetCacheParams
 function retrieves the following cache parameters for the CPU on which it is executed: type of cache (instruction, data, unified), cache level in cache hierarchy, and cache size, in bytes. The function is based on function #4 of the CPUID instruction, and therefore works only for the CPUs that support this function. For old and non-Intel CPUs that do not support this CPUID extension, the function returns the
ippStsCpuNotSupportedErr
 status. It means that cache parameters cannot be obtained with the
ippGetCacheParams
 function and you should use other methods based on a particular CPU specification.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error condition when the
ppCacheInfo
 pointer is
NULL
.
ippStsNotSupportedCpu
Indicates that the processor is not supported.

Example

/*******************************************************************************
* Copyright 2015-2020 Intel Corporation.
*
* This software and the related documents are Intel copyrighted  materials,  and
* your use of  them is  governed by the  express license  under which  they were
* provided to you (License).  Unless the License provides otherwise, you may not
* use, modify, copy, publish, distribute,  disclose or transmit this software or
* the related documents without Intel's prior written permission.
*
* This software and the related documents  are provided as  is,  with no express
* or implied  warranties,  other  than those  that are  expressly stated  in the
* License.
*******************************************************************************/

#include <stdio.h>
#include "ipp.h"

static char* cacheType[] = {
    "Data Cache",
    "Instruction Cache",
    "Unified Cache"
};

int main(){
    IppCache* pCacheInfo;
    int i;
    IppStatus sts;

    sts = ippGetCacheParams( &pCacheInfo );
    if( sts != ippStsNoErr ){
        printf("Intel(R) Integrated Primitives (Intel(R) IPP) function returned error %s\n", ippGetStatusString( sts ));
        return 0;
    }
    i = 0;
    do{
        printf("cache type  = %s\n", cacheType[pCacheInfo[i].type-1] );
        printf("cache level = %d\n", pCacheInfo[i].level );
        printf("cache size  = %d\n", pCacheInfo[i].size );
        printf("+--------------------------------------+\n" );
    } while( pCacheInfo[++i].type > 0 );

    sts = ippGetL2CacheSize( &i );
    printf("\nCache L2 size = %d\n", i );

    return 0;
}

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804