Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

SetFlushToZero

Enables or disables flush-to-zero (FTZ) mode.

Syntax

IppStatus ippSetFlushToZero(int
value
, unsigned int*
pUMask
);
Include Files
ippcore.h
Parameters
value
Switch to set or clear the corresponding bit of the MXCSR register.
  • When
    value
    is not equal to zero, flush-to-zero (FTZ) mode is enabled
  • When
    value
    is set to zero, FTZ mode is disabled
pUMask
Pointer to the current underflow exception mask; may be set to
NULL
.
Description
This function enables FTZ mode for processors that support Intel® Streaming SIMD Extensions [xx] instructions. The FTZ mode controls the masked response to a SIMD floating-point underflow condition. Use this function to improve performance of applications where underflows are common and rounding the underflow result to zero is acceptable.
FTZ mode is possible only when the mask register is in a certain state. The
ippSetFlushToZero
function checks and changes this state if necessary. After disabling the FTZ mode, you can restore the initial mask register state. To do this, declare a variable of
unsigned integer
type in your application and point to it the parameter
pUMask
of the
ippSetFlushToZero
function. The initial state of mask register is saved in this location and can be restored later. If you do not need to restore the initial mask state, then the pointer
pUMask
may be set to
NULL
.
Return Values
ippStsNoErr
Indicates no error.
ippStsCpuNotSupportedErr
Indicates an error condition when the FTZ mode is not supported by the processor.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804