Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

WarpAffineGetBufSize

Calculates the size of the external buffer for the affine transform.

Syntax

IppStatus ipprWarpAffineGetBufSize(IpprVolume
srcVolume
, IpprCuboid
srcVoi
, IpprCuboid
dstVoi
, const double
coeffs[3][4]
, int
nChannel
, int
interpolation
, int*
pSize
);
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
srcVolume
Size of the source volume.
srcVoi
Region of interest of the source volume.
dstVoi
Region of interest of the destination volume.
coeffs
Affine transform matrix.
nChannel
Number of channel or planes, possible value is 1.
interpolation
Type of interpolation, the following values are possible:
  • IPPI_INTER_NN
    -
    nearest neighbor interpolation,
  • IPPI_INTER_LINEAR
    -
    trilinear interpolation,
  • IPPI_INTER_CUBIC
    -
    tricubic interpolation,
  • IPPI_INTER_CUBIC2P_BSPLINE
    -
    B-spline,
  • IPPI_INTER_CUBIC2P_CATMULLROM
    -
    Catmull-Rom spline,
  • IPPI_INTER_CUBIC2P_B05C03
    -
    special two-parameters filter (1/2, 3/10).
pSize
Pointer to the size of the external buffer.
Description
This function calculates the size (in bytes) of the external buffer that is required for the ipprWarpAffine function. (In some cases the function returns zero size of the buffer).
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error when
pSize
or
coeffs
is
NULL
.
ippStsSizeErr
Indicates an error if width, or height, or depth of the
srcVoi
or
dstVoi
is less than, or equal to zero.
ippStsNumChannelErr
Indicates an error when
nChannel
has an illegal value.
ippStsInterpolationErr
Indicates an error when
interpolation
has an illegal value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804