Developer Reference

  • 2020
  • 10/21/2020
  • Public Content
Contents

InpaintGetSize

Computes the size of the state structure and work buffer for image inpainting.

Syntax

IppStatus ippiInpaintGetSize(const Ipp8u*
pMask
, int
maskStep
, IppiSize
roiSize
, Ipp32f
radius
, IppiInpaintFlag
flags
, int
channels
, int*
pStateSize
, int*
pBufSize
);
Include Files
ippcv.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pMask
Pointer to the mask image ROI.
maskStep
Distance, in bytes, between the starting points of consecutive lines in the mask image.
roiSize
Size of the image ROI, in pixels.
radius
Radius of the neghborhood used for inpainting.
flags
Specifies algorithm for image inpainting. Possible values:
IPP_INPAINT_TELEA
Telea algorithm
IPP_INPAINT_NS
Navier-Stokes equation
channels
Number of channels in the image.
pStateSize
Pointer to the size of the state structure.
pBufSize
Pointer to the size of the external work buffer.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function computes the size of the state structure for direct methods of image inpainting and the size of the external work buffer. Call this function before using
ippiInpaintInit
. For an example on how to use this function, refer to the example provided with the
ippiInpaint
function description.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error when width or height of the image is less than, or equal to zero.
ippStsStepErr
Indicates an error when the step in the mask image is too small.
ippStsBadArgErr
Indicates an error when
radius
is less than 1, or
flags
has an illegal value.
ippStsNumChannelsErr
Indicates an error when the specified number of image channels is invalid or not supported.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804