Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

TiltHaarFeatures

Modifies a Haar classifier by tilting specified features.

Syntax

IppStatus ippiTiltHaarFeatures_32f(const Ipp8u*
pMask
, int
flag
, IppiHaarClassifier_32f*
pState
);
IppStatus ippiTiltHaarFeatures_32s(const Ipp8u*
pMask
, int
flag
, IppiHaarClassifier_32s*
pState
);
Include Files
ippcv.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pMask
Pointer to the mask vector.
flag
Flag to choose the direction of feature tilting.
pState
Pointer to the Haar classifier structure.
Description
This function tilts specified features of the Haar classifier.
Before using this function, compute the size of the Haar classifier state structure using HaarClassifierGetSize and initialize the structure using TiltedHaarClassifierInit.
Non-zero elements of previously prepared vector
pMask
indicates the features that are tilted. The
flag
parameter specifies how the features are tilted:
  • if
    flag
    is equal to 0, the feature is tilted around the left top corner clockwise
  • if
    flag
    is equal to 1, the feature is tilted around the bottom left corner counter-clockwise
This mixed classifier containing both common and tilted features can be used by the function
ippiApplyMixedHaarClassifier
.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
.
ippStsBadArgErr
Indicates an error when the classifier is tilted already.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804