Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

FilterColumnPipeline, FilterColumnPipeline_Low

Apply the filter to image columns.

Syntax

Case 1: Operation on integer data
IppStatus ippiFilterColumnPipeline_<mod>(const Ipp<srcDatatype>**
ppSrc
, Ipp<dstDatatype>*
pDst
, int
dstStep
, IppiSize
roiSize
, const Ipp<srcDatatype>*
pKernel
, int
kernelSize
, int
divisor
, Ipp8u*
pBuffer
);
Supported values for
mod
:
16s_C1R
16s8u_C1R
16s8s_C1R
16u_C1R
16s_C3R
16s8u_C3R
16s8s_C3R
16u_C3R
IppStatus ippiFilterColumnPipeline_Low_16s_C1R(const Ipp16s**
ppSrc
, Ipp16s*
pDst
, int
dstStep
, IppiSize
roiSize
, const Ipp16s*
pKernel
, int
kernelSize
, int
divisor
, Ipp8u*
pBuffer
);
IppStatus ippiFilterColumnPipeline_Low_16s_C3R(const Ipp16s**
ppSrc
, Ipp16s*
pDst
, int
dstStep
, IppiSize
roiSize
, const Ipp16s*
pKernel
, int
kernelSize
, int
divisor
, Ipp8u*
pBuffer
);
Case 2: Operation on floating-point data
IppStatus ippiFilterColumnPipeline_<mod>(const Ipp<datatype>**
ppSrc
, Ipp<datatype>*
pDst
, int
dstStep
, IppiSize
roiSize
, const Ipp<datatype>*
pKernel
, int
kernelSize
, Ipp8u*
pBuffer
);
Supported values for
mod
:
32f_C1R
32f_C3R
Include Files
ippcv.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
ppSrc
Double pointer to the source image ROI.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
roiSize
Size of the destination ROI in pixels.
pKernel
Pointer to the strow kernel values.
kernelSize
Size of the kernel in pixels.
divisor
Value by which the computed result is divided (for operations on integer data only).
pBuffer
Pointer to the working buffer.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
The function
ippiFilterColumnPipeline_Low
performs calculation exclusively with the 16s-data, and the input data must be in the range ensuring that the overflow does not occur during calculation and the result can be represented by a 32-bit integer number.
These functions apply the column filter of the separable convolution kernel to the source image
pSrc
. The filter coefficients are placed in the reversed order. For integer data:
and for floating point data:
Here
j = 0, ...
roiSize.width
-1
,
i=0,...
roiSize.height
-1
.
The size of the source image is
(
roiSize.height
+
kernelSize
- 1) *
roiSize.width
.
The functions requires the external buffer
pBuffer
, its size should be previously computed by the functions
ippiFilterColumnPipelineGetBufferSize
and
ippiFilterColumnPipelineGetBufferSize_Low
respectively.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsNullPtrErr
Indicates an error condition if one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with a zero or negative value.
ippStsStepErr
Indicates an error condition if
srcStep
or
dstStep
is less than
roiSize.width
* <
pixelSize
>
ippStsNotEvenStepErr
Indicates an error condition if one of the step values is not divisible by 4 for floating-point images, or by 2 for short-integer images.
ippStsBadArgErr
Indicates an error condition if
divisor
is equal to 0.

Example

/******************************************************************************* * Copyright 2015-2020 Intel Corporation. * * This software and the related documents are Intel copyrighted materials, and * your use of them is governed by the express license under which they were * provided to you (License). Unless the License provides otherwise, you may not * use, modify, copy, publish, distribute, disclose or transmit this software or * the related documents without Intel's prior written permission. * * This software and the related documents are provided as is, with no express * or implied warranties, other than those that are expressly stated in the * License. *******************************************************************************/ // An example of performing The code example shows how these functions can be used to organize the separable convolution as a step of // image processing pipeline.implemented with Intel(R) Integrated Primitives (Intel(R) IPP) functions : // ippiFilterRowBorderPipelineGetBufferSize_Low_16s_C1R // ippiFilterColumnPipeline_Low_16s_C1R // ippiFilterColumnPipelineGetBufferSize_Low_16s_C1R // ippiFilterRowBorderPipeline_Low_16s_C1R #include <stdio.h> #include "ipp.h" #define WIDTH 128 /* image width */ #define HEIGHT 64 /* image height */ /* Next two defines are created to simplify code reading and understanding */ #define EXIT_MAIN exitLine: /* Label for Exit */ #define check_sts(st) if((st) != ippStsNoErr) goto exitLine; /* Go to Exit if Intel(R) IPP function returned status different from ippStsNoErr */ /* Results of ippMalloc() are not validated because Intel(R) IPP functions perform bad arguments check and will return an appropriate status */ int main(void) { IppStatus status = ippStsNoErr; const Ipp16s **pGet = NULL; Ipp16s* src = NULL, *dst = NULL; int kernelSize = 3; int xAnchor = kernelSize >> 1; /* The anchor value, (0 <= xAnchor < kernelSize) */ Ipp16s pKerX[3] = { 1, 2, 1 }, pKerY[3] = { 1, 0, 1 }; /* The pointer to the kernels */ Ipp16s* pSrc = NULL, *pDst = NULL; /* Pointers to source/destination images */ int srcStep = 0, dstStep = 0; /* Steps, in bytes, through the source/destination images */ IppiSize roiSize = { WIDTH, HEIGHT }; /* Size of source/destination ROI in pixels */ IppiSize roi = { WIDTH, 1 }; /* Size of destination ROI in pixels */ int divisor = 1; /* The value to divide output pixels by */ Ipp8u borderValue = 0; Ipp8u *pBufRow = NULL, *pBufCol = NULL;/* Pointer to the work buffer */ int sizeRow = 0, sizeCol = 0; /* Common work buffer size */ int todo = roiSize.height, bufLen; int mStep = (roiSize.width + 7)&(~7); int sStep = 0, dStep = 0; bufLen = mStep * 3 *sizeof(Ipp16s) + 4*sizeof(Ipp16s*); pGet = (const Ipp16s**)ippsMalloc_8u(bufLen); pSrc = ippiMalloc_16s_C1(roiSize.width, roiSize.height, &srcStep); pDst = ippiMalloc_16s_C1(roiSize.width, roiSize.height, &dstStep); dst = pDst; src = pSrc; sStep = srcStep >> 1, dStep = dstStep >> 1; pGet[0] = pGet[1] = (Ipp16s*)(pGet + 4); pGet[2] = pGet[1] + mStep; pGet[3] = pGet[2] + mStep; check_sts( status = ippiFilterRowBorderPipelineGetBufferSize_Low_16s_C1R(roiSize, 3, &sizeRow) ) check_sts( status = ippiFilterColumnPipelineGetBufferSize_Low_16s_C1R(roiSize, 3, &sizeCol) ) pBufRow = ippsMalloc_8u(sizeRow); pBufCol = ippsMalloc_8u(sizeCol); check_sts( status = ippiFilterRowBorderPipeline_Low_16s_C1R(pSrc, srcStep, ( Ipp16s**)pGet, roi, pKerX, kernelSize, xAnchor, ippBorderRepl, borderValue, divisor, pBufRow) ) todo--; if (todo==0) { pGet[2] = pGet[0]; } else { pGet[2] = pGet[0] + mStep; pGet[3] = pGet[2] + mStep; for (; todo>0;src += sStep, dst += dStep, todo--) { check_sts( status = ippiFilterRowBorderPipeline_Low_16s_C1R(src, srcStep, (Ipp16s**)(pGet + 2), roi, pKerX, kernelSize, xAnchor, ippBorderRepl, borderValue, divisor, pBufRow) ) check_sts( status = ippiFilterColumnPipeline_Low_16s_C1R(pGet, dst, dstStep, roi, pKerY, kernelSize, divisor, pBufCol) ) pGet[0] = pGet[1]; pGet[1] = pGet[2]; pGet[2] = pGet[3]; pGet[3] = pGet[0]; } } check_sts( status = ippiFilterColumnPipeline_Low_16s_C1R(pGet, dst, dstStep, roi, pKerY, kernelSize, divisor, pBufCol) ) EXIT_MAIN ippiFree(pSrc); ippsFree(pBufRow); ippsFree(pBufCol); ippiFree(pDst); printf("Exit status %d (%s)\n", (int)status, ippGetStatusString(status)); return (int)status; }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804