Developer Reference

  • 2020
  • 10/21/2020
  • Public Content
Contents

Not

Performs a bitwise NOT operation on each pixel of a source buffer.

Syntax

Case 1: Not-in-place operation
IppStatus ippiNot_<mod>
(
const Ipp8u*
pSrc
,
int
srcStep
,
Ipp8u*
pDst
,
int
dstStep
,
IppiSize
roiSize
);
Supported values for
mod
:
8u_C1R
8u_C3R
8u_C4R
8u_AC4R
Case 2: In-place operation
IppStatus ippiNot_<mod>
(
Ipp8u*
pSrcDst
,
int
srcDstStep
,
IppiSize
roiSize
);
Supported values for
mod
:
8u_C1IR
8u_C3IR
8u_C4IR
8u_AC4IR
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source image ROI.
srcStep
Distance in bytes between starts of consecutive lines in the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
pSrcDst
Pointer to the source and destination image ROI for the in-place operation.
srcDstStep
Distance in bytes between starts of consecutive lines in the source and destination image for the in-place operation.
roiSize
Size of the source and destination ROI in pixels.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function performs a bitwise NOT operation on each pixel value of a source image ROI.
Note that the functions with the
AC4
descriptor do not process alpha channels.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with zero or negative value.
ippStsStepErr
Indicates an error condition if
srcStep
,
dstStep
, or
srcDstStep
has a zero or negative value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804