Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

CbYCr422ToBGR

Converts 16-bit per pixel CbYCr image to four channel BGR image.

Syntax

IppStatus ippiCbYCr422ToBGR_8u_C2C4R(const Ipp8u*
pSrc
, int
srcStep
, Ipp8u*
pDst
, int
dstStep
, IppiSize
roiSize
, Ipp8u
aval
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrc
Pointer to the source image ROI.
srcStep
Distance in bytes between starts of consecutive lines in the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
roiSize
Size of the source and destination ROI in pixels.
aval
Constant value to create the fourth channel.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function converts the
Cb'Y'Cr'
image
pSrc
, packed in
4:2:2 sampling
format, to the four channel gamma-corrected
B'G'R'
image
pDst
according to the same formulas as the function
ippiYCbCrToRGB
does.
A
CbYCr
image has the following sequence of bytes:
Cb0Y0Cr0Y1
,
Cb1Y2Cr1Y3
, ... .
The output
B'G'R'
values are saturated to the range [0..255].
The fourth channel is created by setting channel values to the constant value
aval
.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if
pSrc
or
pDst
is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with a zero or negative value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804