Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

YCbCr420ToBGR

Converts a YCbCr image with the 4:2:0 sampling to the BGR image.

Syntax

IppStatus ippiYCbCr420ToBGR_8u_P3C3R(const Ipp8u*
pSrc
[3], int
srcStep
[3], Ipp8u*
pDst
, int
dstStep
, IppiSize
roiSize
);
IppStatus ippiYCbCr420ToBGR_8u_P3C4R(const Ipp8u*
pSrc
[3], int
srcStep
[3],Ipp8u*
pDst
, int
dstStep
, IppiSize
roiSize
, Ipp8u
aval
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrc
An array of pointers to ROI in separate planes of the source image.
srcStep
An array of distances in bytes between starts of consecutive lines in the source image planes.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
roiSize
Size of the source and destination ROI in pixels.
aval
Constant value to create fourth channel.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function converts the
Y'Cb'Cr'
image
pSrc
with the
4:2:0 sampling
(see Table
“Planar Image Formats”
for more details) to the gamma-corrected three- or four-channel
B'G'R'
image
pDst
. The conversion is performed according to the same formulas as the function
ippiYCbCrToRGB
does.
Fourth channel is created by setting channel values to the constant value
aval
.
The values of
roiSize.width
and
roiSize.height
should be multiples of 2. If not the function reduces their original values to the nearest multiples of 2, performs operation, and returns warning message.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if
pSrc
or
pDst
is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with a zero or negative value.
ippStsDoubleSize
Indicates a warning if
roiSize
has a field that is not a multiple of 2.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804