Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

YCbCr422ToGray

Converts an interlaced 4:2:2 YCbCr or YCrCb image to gray-scale extracting luminance (Y) component.

Syntax

IppStatus ippiYCbCr422ToGray_8u_C2C1R(const Ipp8u*
pSrc
, int
srcStep
, Ipp8u*
pDst
, int
dstStep
, IppiSize
roiSize
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrc
Pointer to the source image ROI.
srcStep
Distance, in bytes, between the starting points of consecutive lines in the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance, in bytes, between the starting points of consecutive lines in the destination image.
roiSize
Size of the source and destination ROI in pixels.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function converts an interlaced
Y'Cb'Cr'
or
Y'Cr'Cb'
image
pSrc
with the 4:2:2 sampling (see Table
“Pixel-Order Image Formats”
and Table
“Planar Image Formats”
for more details) to the gray-scale image
pDst
extracting luminance (Y) component.
Y'Cb'Cr'
image with 4:2:2 sampling is also known as YUY2 format, and
Y'Cr'Cb'
as YVYU.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if
pSrc
or
pDst
is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with a zero or negative value.

Example

The code example below demonstrates how to use the
ippiYCbCr422ToGray_8u_C2C1R
function.
const int WIDTH = 2; const int HEIGHT = 2; Ipp8u pSrc[WIDTH * HEIGHT * 2] = { 190,70,191,80, 200,71,201,81, }; Ipp8u pDst[WIDTH * HEIGHT]; int srcStep = WIDTH * 2, dstStep = WIDTH; IppiSize roiSize = {WIDTH, HEIGHT}; IppStatus status = ippiYCbCr422ToGray_8u_C2C1R(pSrc, srcStep, pDst, dstStep, roiSize); if ( status == ippStsNoErr) printf("PASS:\n%3d %3d\n%3d %3d\n", pDst[0], pDst[1], pDst[2], pDst[3]); else printf("FAIL: status = %d\n", status);
Result:
PASS: 190 191 200 201

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804