Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

YCbCr411ToYCrCb420

Converts 4:1:1 YCbCr image to 4:2:0 YCrCb image.

Syntax

IppStatus ippiYCbCr411ToYCrCb420_8u_P2P3R(const Ipp8u*
pSrcY
, int
srcYStep
, const Ipp8u*
pSrcCbCr
, int
srcCbCrStep
, Ipp8u*
pDst
[3], int
dstStep
[3], IppiSize
roiSize
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrcY
Pointer to the ROI in the luminance plane of the source image.
srcYStep
Distance in bytes between starts of consecutive lines in the luminance plane of the source image.
pSrcCbCr
Pointer to the ROI in the interleaved chrominance plane of the source image.
srcCbCrStep
Distance in bytes between starts of consecutive lines in the interleaved chrominance plane of the source image.
pDst
Array of pointers to the ROI in each plane of the destination image.
dstStep
Array of distances in bytes between starts of consecutive lines in each plane of the destination image.
roiSize
Size of the ROI in pixels, its width should be multiple of 4, its height should be multiple of 2.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function converts the
4:1:1
two-plane source image
pSrc
to the
4:2:0
three-plane image
pDst
with a different order of components. The first plane of the source image
pSrcY
contains luminance samples
Y0
,
Y1
,
Y2
, ..., the second plane
pSrcCbCr
contains interleaved chrominance samples
Cb0
,
Cr0
,
Cb1
,
Cr1
, ... .The destination image has the following order of pointers:
Y
-plane,
Cr
-plane,
Cb
-plane (see Table
“Planar Image Formats”
),
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize.width
is less than 4 or
roiSize.height
is less than 2.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804