Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

YCbCr422To420_Interlace

Converts interlaced YCbCr image from 4:2:2 sampling format to 4:2:0 format.

Syntax

IppStatus ippiYCbCr422To420_Interlace_8u_P3R(const Ipp8u*
pSrc
[3], int
srcStep
[3], Ipp8u*
pDst
[3], int
dstStep
[3], IppiSize
roiSize
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrc
Array of pointers to the ROI in each plane for source image.
srcStep
Array of distances in bytes between starts of consecutive lines in each plane for the source image.
pDst
Array of pointers to the ROI in each plane for destination image.
dstStep
Array of distances in bytes between starts of consecutive lines in each plane fore destination image.
roiSize
Size of the source and destination ROI in pixels, its width must be multiple of 2, and height must be multiple of 4.
Description
This function operates with ROI (see Regions of Interest in Intel IPP ).
This function converts the interlaced
4:2:2
image
pSrc
to the
4:2:0
image
pDst
(see Table
“Planar Image Formats”
).
The conversion is performed in accordance with the following formulas:
Y1
dest
= Y1
src
;
Cb0(Cr0)
dest
= (3*Cb0(Cr0)
src
+ Cb2(Cr2)
src
+ 2)/4;
Cb1(Cr1)
dest
= (Cb1(Cr1)
src
+ 3*Cb3(Cr3)
src
+ 2)/4;
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize.width
is less than 2, or
roiSize.height
is less than 4.
ippStsDoubleSize
Indicates a warning if
roiSize.width
is not multiple of 2, or
roiSize.height
is not multiple of 4.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804