Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

YCrCb420ToCbYCr422

Converts 4:2:0 YCrCb image to 4:2:2 CbYCr image.

Syntax

IppStatus ippiYCrCb420ToCbYCr422_8u_P3C2R(const Ipp8u*
pSrc
[3], int
srcStep
[3], Ipp8u*
pDst
, int
dstStep
, IppiSize
roiSize
);
Include Files
ippcc.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSrc
Array of pointers to the ROI in each plane of the source image.
srcStep
Array of distances in bytes between starts of consecutive lines in each plane of the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
roiSize
Size of the source and destination ROI in pixels, height and width should be multiple of 2.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function converts the
4:2:0
YCrCb
three-plane image
pSrc
(see Table
“Planar Image Formats”
) to the
4:2:2
CbYCr
two-channel image
pDst
with the following sequence of samples:
Cb0
,
Y0
,
Cr0
,
Y1
,
Cb1
,
Y2
,
Cr1
,
Y3
,
Cb2
, ... (see Table
“Pixel-Order Image Formats”
).
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsNullPtrErr
Indicates an error condition if any of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error condition if any field of the
roiSize
is less than 2.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804