Intel® Integrated Performance Primitives Developer Reference

Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

CopyManaged

Copies pixel values between two images in accordance with the specified type of copying.

Syntax

IppStatus ippiCopyManaged_8u_C1R
(
const Ipp8u*
pSrc
,
int
srcStep
,
Ipp8u*
pDst
,
int
dstStep
,
IppiSize
roiSize
,
int
flags
);
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source image ROI.
srcStep
Distance, in bytes, between the starting points of consecutive lines in the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance, in bytes, between the starting points of consecutive lines in the destination image.
roiSize
Size of the image ROI in pixels.
flags
Specifies the type of copying. Possible values are:
  • IPP_TEMPORAL_COPY
     - standard copying
  • IPP_NONTEMPORAL_STORE
     - copying without caching the destination image
  • IPP_NONTEMPORAL_LOAD
     - processor uses non-temporal load instructions
Description
This function operates with ROI.
This function copies data from a source image ROI
pSrc
 to the destination image ROI
pDst
. The
flags
 parameter specifies the type of copying that the function performs:
  • When
    flags
     is set to
    IPP_TEMPORAL_COPY
    , the function is identical to the
    ippiCopy_8u_C1R
     function.
  • When
    flags
     is set to
    IPP_NONTEMPORAL_STORE
    , the processor uses non-temporal store instructions. Copying is performed without caching the data of the destination image.
  • When
    flags
     is set to
    IPP_NONTEMPORAL_LOAD
    , the processor uses non-temporal load instructions.
To achieve better performance, align data to 64-byte boundary.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error when
roiSize
 has a field with a zero or negative value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804