Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

ZigzagFwd8x8

Converts a conventional order to the zigzag order.

Syntax

IppStatus ippiZigzagFwd8x8_16s_C1
(
const
Ipp16s*
pSrc
,
Ipp16s*
pDst
);
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source data.
pDst
Pointer to the destination data.
Description
This function rearranges data in an 8x8 block from a conventional order (left-to-right, top-to-bottom) to the zigzag sequence.
Figure Zigzag Sequence specifies the resulting zigzag sequence.
Zigzag Sequence
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when any of the specified pointers is
NULL
.

Example

The code example below shows how to use the
ippiZigzagFwd8x8_16s_C1
function.
Ipp16s src[8*8] = { 0, 1, 5, 7, 9, 2, 4, 1, 5, 4, 8, 6, 3, 8, 0, 3, 6, 2, 6, 8, 1, 4, 2, 8, 4, 3, 2, 9, 3, 0, 6, 6, 7, 7, 3, 0, 4, 1, 0, 9, 5, 1, 9, 2, 5, 7, 1, 7, 0, 3, 5, 0, 7, 5, 9, 8, 2, 9, 1, 4, 6, 8, 2, 3 }; Ipp16s dst[8*8]; ippiZigzagFwd8x8_16s_C1 ( src, dst ); Result: 0 1 5 7 9 2 4 1 5 4 8 6 3 8 0 3 6 2 6 8 1 4 2 8 4 3 2 9 3 0 6 6 src //conventional order 7 7 3 0 4 1 0 9 5 1 9 2 5 7 1 7 0 3 5 0 7 5 9 8 2 9 1 4 6 8 2 3 0 1 5 6 4 5 7 8 2 4 7 3 6 6 9 2 3 8 2 7 5 0 1 3 9 1 8 4 1 0 4 3 dst //zigzag order 0 9 3 2 9 5 2 4 0 2 3 8 6 1 5 0 1 4 7 7 0 6 9 1 5 6 8 9 7 8 2 3

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804