Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

GetAffineQuad

Computes vertex coordinates of the quadrangle, to which the source ROI rectangle is mapped by the affine transform.

Syntax

IppStatus ippiGetAffineQuad (IppiRect
srcRoi
, double
quad
[4][2], const double
coeffs
[2][3]
);
IppStatus ippiGetAffineQuad_L(IppiRectL
srcRoi
, double
quad
[4][2], const double
coeffs
[2][3]
);
Include Files
ippi.h
Flavors with the
_L
suffix:
ippi_l.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
srcRoi
Region of interest in the source image (of the
IppiRect
type).
quad
Output array. Contains vertex coordinates of the quadrangle, to which the source ROI is mapped by the affine transform function.
coeffs
The given affine transform coefficients.
Description
This function operates with ROI (see ROI Processing in Geometric Transforms ).
This function is used as a support function for . It computes vertex coordinates of the quadrangle, to which the source rectangular ROI is mapped by the affine transform function using the given coefficients
coeffs
.
The first dimension [4] of the array
quad
[4][2]
is equal to the number of vertices, and the second dimension
[2]
means
x
and
y
coordinates of the vertex. Quadrangle vertices have the following meaning:
quad
[0]
corresponds to the transformed top-left corner of the source ROI,
quad
[1]
corresponds to the transformed top-right corner of the source ROI,
quad
[2]
corresponds to the transformed bottom-right corner of the source ROI,
quad
[3]
corresponds to the transformed bottom-left corner of the source ROI.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsCoeffErr
Indicates an error condition if c
00
*c
11
- c
01
*c
10
= 0.
ippStsSizeErr
Indicates an error condition if
srcRoi
has a size field with zero or negative value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804