Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DCT8x8Fwd

Performs a forward DCT on a 2D buffer of 8x8 size.

Syntax

Case 1: Not-in-place operation
IppStatus ippiDCT8x8Fwd_<mod>(const Ipp<datatype>*
pSrc
, Ipp<datatype>*
pDst
);
Supported values for
mod
:
16s_C1
32f_C1
Case 2: Not-in-place operation with ROI
IppStatus ippiDCT8x8Fwd_<mod>(const Ipp<srcDatatype>*
pSrc
, int
srcStep
, Ipp<dstDatatype>*
pDst
);
Supported values for
mod
:
16s_C1R
8u16s_C1R
Case 3: In-place operation
IppStatus ippiDCT8x8Fwd_<mod>(Ipp<datatype>*
pSrcDst
);
Supported values for
mod
:
16s_C1I
32f_C1I
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source image buffer.
srcStep
Distance in bytes between starts of consecutive lines in the source image buffer for operations with ROI.
pDst
Pointer to the destination image buffer.
pSrcDst
Pointer to the source and destination image for in-place operations.
Description
Some flavors operate with ROI (see Regions of Interest in Intel IPP).
This function computes the forward discrete cosine transform of short integer or floating-point data in a 2D buffer of 8x8 size. No prerequisites are needed to use this transform function.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if
pSrc, pDst,
or
pSrcDst
pointer is
NULL
.
ippStsStepErr
Indicates an error condition if
srcStep
value is zero or negative.

Example

The code example below illustrates the use of
ippiDCT8x8Fwd
function.
IppStatus dct16s( void ) {
Ipp16s x[64] = {0};
IppiSize roi = {8,8};
int i;
for( i=0; i<8; ++i ) {
ippiSet_16s_C1R( (Ipp16s)i, x+8*i+i, 8*sizeof(Ipp16s), roi );
--roi.width;
--roi.height;
}
return ippiDCT8x8Fwd_16s_C1I( x );
}
The destination image
x
contains:
18 -9 -2 -1 -1 0 0 0
-9 7 0 0 0 0 0 0
-2 0 2 0 0 0 0 0
-1 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
 

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804