Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

DCT8x8To2x2Inv, DCT8x8To4x4Inv

Perform an inverse DCT on a 2D buffer of 8x8 size with further downsampling to 2x2 or 4x4 size.

Syntax

IppStatus ippiDCT8x8To2x2Inv_16s_C1(const Ipp16s*
pSrc
, Ipp16s*
pDst
);
IppStatus ippiDCT8x8To4x4Inv_16s_C1(const Ipp16s*
pSrc
, Ipp16s*
pDst
);
IppStatus ippiDCT8x8To2x2Inv_16s_C1I(Ipp16s*
pSrcDst
);
IppStatus ippiDCT8x8To4x4Inv_16s_C1I(Ipp16s*
pSrcDst
);
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source image.
pDst
Pointer to the destination buffer.
pSrcDst
Pointer to the source and destination buffer for in-place operations.
Description
These functions compute the inverse discrete cosine transform of the 2D buffer
pSrc
of 8x8 size. Then the functions perform downsampling of the result by averaging to the destination buffer
pDst
of size 2x2 or 4x4.
In-place flavors of the functions perform operations on the source and destination buffer
pSrcDst
.
Source data for 16s flavors must be the result of the forward discrete cosine transform of data from the range [-256, 255], they cannot be arbitrary data from the range [-32768, 32767].
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error.
ippStsNullPtrErr
Indicates an error condition if one of the specified pointers is
NULL
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804