Developer Reference

  • 2020
  • 07/15/2020
  • Public Content
Contents

Erode3x3

Performs erosion of an image using a 3x3 mask.

Syntax

IppStatus ippiErode3x3_64f_C1R(const Ipp64f*
pSrc
, int
srcStep
, Ipp64f*
pDst
, int
dstStep
, IppiSize
roiSize
);
Include Files
ippi.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
Parameters
pSrc
Pointer to the source image ROI.
srcStep
Distance in bytes between starts of consecutive lines in the source image.
pDst
Pointer to the destination image ROI.
dstStep
Distance in bytes between starts of consecutive lines in the destination image.
roiSize
Size of the source and destination ROI in pixels.
Description
This function operates with ROI (see Regions of Interest in Intel IPP).
This function performs erosion of a rectangular ROI area inside a 2D image using a symmetric 3x3 mask.
Source and destination images can have different size, but the ROI size is the same for both images. The output pixel is set to the minimum of the corresponding input pixel and its 8 neighboring pixels.
Return Values
ippStsNoErr
Indicates no error. Any other value indicates an error or a warning.
ippStsNullPtrErr
Indicates an error condition if
pSrc
or
pDst
is
NULL
.
ippStsSizeErr
Indicates an error condition if
roiSize
has a field with a zero or negative value.
ippStsStepErr
Indicates an error condition if
srcStep
or
dstStep
has a zero or negative value.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804