Developer Reference

  • 2020
  • 10/21/2020
  • Public Content
Contents

MorphAdvInit

Initializes the specification structure for advanced morphological operations.

Syntax

IppStatus ippiMorphAdvInit_<mod>(IppiSize
roiSize
, const Ipp8u*
pMask
, IppiSize
maskSize
, IppiMorphAdvState*
pSpec
, Ipp8u*
pBuffer
);
Supported values for
mod
:
1u_C1R
8u_C1R
16u_C1R
16s_C1R
32f_C1R
8u_C3R
32f_C3R
8u_C4R
32f_C4R
Include Files
ippcv.h
Domain Dependencies
Headers:
ippcore.h
,
ippvm.h
,
ipps.h
,
ippi.h
Libraries:
ippcore.lib
,
ippvm.lib
,
ipps.lib
,
ippi.lib
Parameters
pSpec
Pointer to the specification structure.
roiSize
Maximal size of the image ROI (in pixels) that can be processed using the allocated structure.
pMask
Pointer to the mask.
maskSize
Size of the mask in pixels.
pBuffer
Pointer to the external buffer for advanced morphological operations.
Description
This function operates with ROI.
This function initializes the specification structure
pSpec
in the external buffer. This structure is used by the MorphOpenBorder and MorphCloseBorder functions that perform open and close morphological operations.
All advanced morphological operations are performed on the source image pixels corresponding to non-zero values of the structuring element (mask)
pMask
.
This function required that the image ROI does not exceed the maximum width and height
roiSize
specified by the initialization functions.
For an example on how to use this function, see the code example provided with the MorphCloseBorder function description.
Return Values
ippStsNoErr
Indicates no error.
ippStsNullPtrErr
Indicates an error when one of the specified pointers is
NULL
.
ippStsSizeErr
Indicates an error when
maskSize
has a field with a zero or negative value, or if
roiWidth
is less than 1.
ippStsAnchorErr
Indicates an error when
anchor
is outside the mask.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804