API Quick Reference Guide

  • 2020
  • 09/30/2019
  • Public Content
Contents

iwiMul

Syntax

typedef struct _IwiMulParams { IppHintAlgorithm algoMode; int scaleFactor; IwiChDescriptor chDesc; } IwiMulParams;
static IW_INLINE void iwiMul_SetDefaultParams( IwiMulParams *pParams )
IW_DECL(IppStatus) iwiMul( const IwiImage *pSrc1Image, const IwiImage *pSrc2Image, IwiImage *pDstImage, const IwiMulParams *pAuxParams, const IwiTile *pTile );
Parameters
pSrc1Image
Pointer to the first multiplied image.
pSrc2Image
Pointer to the second multiplied image.
pDstImage
Pointer to the resulting image (can be the same as
pSrc2Image
).
pAuxParams
Pointer to the auxiliary parameters structure. If
NULL
, default parameters are used.
pTile
Pointer to the
IwiTile
structure for tiling. If
NULL
, the whole image is processed.
Auxiliary Arguments
Argument
Default Value
Description
algoMode
IppAlgHintNone
Accuracy mode.
scaleFactor
0
Scale factor.
chDesc
iwiChDesc_None
IwiChDescriptor
value.
Description
This function multiplies one image by another and puts the resulting image to
pDstImage
.
This function supports the following features:
Feature
Support
In-place mode
Yes
64-bit sizes
Yes
Internal threading
No
Manual tiling
Yes
IwsTile
simple tiling
Yes
IwsTile
pipeline tiling
Yes
Return Values
ippStsDataTypeErr
The
dataType
value is illegal.
ippStsNumChannelsErr
The value for channels is illegal.
ippStsSizeErr
Values for size fields are illegal.
ippStsNullPtrErr
At least one of the pointers (except
pTile
) is
NULL
.
ippStsNoErr
No errors.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804