• 2019 Update 3
  • 03/07/2019
  • Public Content
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Contents

Intel® Trace Analyzer can display and analyze general (properly nested) state changes, relating to function calls, entry/exit to/from code regions and other events occurring in a process. Intel® Trace Analyzer implements a two-level model of states: a state is referred to by an activity name that identifies a group of states, and the state (or symbol) name that references a particular state in that group. For instance, all MPI functions are part of the activity MPI, and each one is identified by its function name, for instance
MPI_Send
for C and for Fortran.
The Intel® Trace Collector API allows the user to define arbitrary activities and symbols and to record entry and exit to/from them. In order to reduce the instrumentation overhead, symbols are referred to by integer handles that can be managed automatically (using the
VT_funcdef()
interface) or assigned by the user (using the old
VT_symdef()
function). All activities and symbols are defined by each process that uses them, but it is not necessary to define them consistently on all processes (see
UNIFY-SYMBOLS
).
Optionally, information about source locations can be recorded for state enter and exit events by passing a non-null location handle to the
VT_enter()
/
VT_leave()
or
VT_beginl()
/
VT_endl()
functions.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804