• 2019 Update 3
  • 03/07/2019
  • Public Content
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The CPU timer described in CPU Cycle Counter is applicable for homogenous systems only. Specifically, the CPU frequency should match across the systems.
For heterogeneous systems with different CPU frequencies, a special
Normalized CPU timer
) can be used. This timer is based on the
Timer Stamp Counter
(TSC) CPU ticks as well as the original CPU timer (
). The normalized timer converts the local CPU ticks into microseconds on the fly to allow usage of TSC on heterogeneous systems.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804