• 2019 Update 3
  • 03/07/2019
  • Public Content
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For distributed memory checking (
) and detecting illegal accesses to memory owned by MPI (
) it is necessary to run all MPI processes under control of the Valgrind* memory checker (version 3.2.0 or higher). See
for more information.
To run Valgrind, invoke it directly on the main MPI process and add the
mpirun -l
option. This way all output printed by Valgrind is automatically prefixed with the MPI process rank. Intel® Trace Collector detects that
is in effect and then leaves adding the rank prefix to
also for Intel® Trace Collector output.
check causes Valgrind reports not only for illegal application accesses (as desired) but also for Intel® MPI Library own access to the locked memory (not desired, because MPI currently owns it and must read or write it). These reports are normal and the Valgrind suppression file in Intel® Trace Collector lib folder tells Valgrind to not print them, but Valgrind must be notified about it through its
When the MPI executable is given on the command line, an MPI application could be started under Valgrind like this:
$ mpirun -check_mpi -l -n <num procs> $ valgrind --suppressions=$VT_LIB_DIR/impi.supp <application> ...
When a wrapper script is used, then it might be possible to trace through the wrapper script by adding the
option, but that could lead to reports about the script interpreter and other programs, so adding Valgrind to the actual invocation of the MPI binary is easier.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804