• 2019 Update 3
  • 03/07/2019
  • Public Content
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By default, Intel® Trace Collector stores names for well-known communicators in the trace:
COMM_WORLD
,
COMM_SELF_#0
,
COMM_SELF_#1
and so on. When new communicators are created, their names are composed of a prefix, a space and the name of the old communicator. For example, calling
MPI_Comm_dup()
on
MPI_COMM_WORLD
will lead to a communicator called
DUP COMM_WORLD
.
There are the following prefixes for MPI functions:
MPI Function
Prefix
MPI_Comm_create()
CREATE
MPI_Comm_dup()
DUP
MPI_Comm_split()
SPLIT
MPI_Cart_sub()
CART_SUB
MPI_Cart_create()
CART_CREATE
MPI_Graph_create()
GRAPH_CREATE
MPI_Intercomm_merge()
MERGE
MPI_Intercomm_merge()
is special because the new communicator is derived from two communicators, not just one as in the other functions. The name of the new inter-communicator will be
MERGE <old name 1>/<old name 2>
if the two existing names are different, otherwise it will be just
MERGE <old name>
.
In addition to these automatically generated names, Intel® Trace Collector also intercepts
MPI_Comm_set_name()
and then uses the name provided by the application. Only the last name set with this function is stored in the trace for each communicator. Derived communicators always use the name that is currently set in the old communicator when the new communicator is created.
Intel® Trace Collector does not attempt to synchronize the names set for the same communicator in different processes, therefore the application has to set the same name in all processes to ensure that this name is really used by Intel® Trace Collector.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804