Developer Reference

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cblas_?gemm_alloc

Allocates storage for a packed matrix (deprecated).

Syntax

float* cblas_sgemm_alloc
(
const
CBLAS_IDENTIFIER
identifier
,
const
MKL_INT
m
,
const
MKL_INT
n
,
const
MKL_INT
k
);
double* cblas_dgemm_alloc
(
const
CBLAS_IDENTIFIER
identifier
,
const
MKL_INT
m
,
const
MKL_INT
n
,
const
MKL_INT
k
);
Include Files
  • mkl.h
Description
The
cblas_?gemm_alloc
routine is one of a set of related routines that enable use of an internal packed storage. Call the
cblas_?gemm_alloc
routine first to allocate storage for a packed matrix structure to be used in subsequent calls, ultimately to compute
C
:=
alpha
*op(
A
)*op(
B
) +
beta
*
C
,
where:

    op(
    X
    )
    is one of the operations
    op(
    X
    ) =
    X
    ,
    op(
    X
    ) =
    X
    T
    , or
    op(
    X
    ) =
    X
    H
    ,

    alpha
    and
    beta
    are scalars,

    A
    ,
    B
    , and
    C
    are matrices:

    op(
    A
    )
    is an
    m
    -by-
    k
    matrix,

    op(
    B
    )
    is a
    k
    -by-
    n
    matrix,

    C
    is an
    m
    -by-
    n
    matrix.

The
cblas_?gemm_alloc
routine is not supported on Windows* OS for the IA-32 architecture with single dynamic library linking.
Input Parameters
identifier
Specifies which matrix is to be packed:
If
identifier
=
CblasAMatrix
, the routine allocates storage to pack matrix
A
.
If
identifier
=
CblasBMatrix
, the routine allocates storage to pack matrix
B
.
m
Specifies the number of rows of matrix op(
A
) and of the matrix
C
. The value of
m
must be at least zero.
n
Specifies the number of columns of matrix op(
B
) and the number of columns of matrix
C
. The value of
n
must be at least zero.
k
Specifies the number of columns of matrix op(
A
) and the number of rows of matrix op(
B
). The value of
k
must be at least zero.
Return Values
The function returns the allocated storage.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804