Developer Reference

Contents

mkl_?bsrtrsv

Triangular solver with simplified interface for a sparse matrix stored in the BSR format (3-array variation) with one-based indexing (deprecated).

Syntax

void
mkl_sbsrtrsv
(
const
char
*uplo
,
const
char
*transa
,
const
char
*diag
,
const
MKL_INT
*m
,
const
MKL_INT
*lb
,
const
float
*a
,
const
MKL_INT
*ia
,
const
MKL_INT
*ja
,
const
float
*x
,
float
*y
);
void
mkl_dbsrtrsv
(
const
char
*uplo
,
const
char
*transa
,
const
char
*diag
,
const
MKL_INT
*m
,
const
MKL_INT
*lb
,
const
double
*a
,
const
MKL_INT
*ia
,
const
MKL_INT
*ja
,
const
double
*x
,
double
*y
);
void
mkl_cbsrtrsv
(
const
char
*uplo
,
const
char
*transa
,
const
char
*diag
,
const
MKL_INT
*m
,
const
MKL_INT
*lb
,
const
MKL_Complex8
*a
,
const
MKL_INT
*ia
,
const
MKL_INT
*ja
,
const
MKL_Complex8
*x
,
MKL_Complex8
*y
);
void
mkl_zbsrtrsv
(
const
char
*uplo
,
const
char
*transa
,
const
char
*diag
,
const
MKL_INT
*m
,
const
MKL_INT
*lb
,
const
MKL_Complex16
*a
,
const
MKL_INT
*ia
,
const
MKL_INT
*ja
,
const
MKL_Complex16
*x
,
MKL_Complex16
*y
);
Include Files
  • mkl.h
Description
This routine is deprecated. Use mkl_sparse_?_trsvfrom the
Intel® MKL
Inspector-executor Sparse BLAS interface instead.
The
mkl_?bsrtrsv
routine solves a system of linear equations with matrix-vector operations for a sparse matrix stored in the BSR format (3-array variation) :
y
:=
A
*
x
or
y
:=
A
T
*
x
,
where:
x
and
y
are vectors,
A
is a sparse upper or lower triangular matrix with unit or non-unit main diagonal,
A
T
is the transpose of
A
.
This routine supports only one-based indexing of the input arrays.
Input Parameters
uplo
Specifies the upper or low triangle of the matrix
A
is used.
If
uplo
=
'U'
or
'u'
, then the upper triangle of the matrix
A
is used.
If
uplo
=
'L'
or
'l'
, then the low triangle of the matrix
A
is used.
transa
Specifies the operation.
If
transa
=
'N'
or
'n'
, then the matrix-vector product is computed as
y
:=
A
*
x
If
transa
=
'T'
or
't'
or
'C'
or
'c'
, then the matrix-vector product is computed as
y
:=
A
T
*
x
.
diag
Specifies whether
A
is a unit triangular matrix.
If
diag
=
'U'
or
'u'
, then
A
is a unit triangular.
If
diag
=
'N'
or
'n'
, then
A
is not a unit triangular.
m
Number of block rows of the matrix
A
.
lb
Size of the block in the matrix
A
.
a
Array containing elements of non-zero blocks of the matrix
A
. Its length is equal to the number of non-zero blocks in the matrix
A
multiplied by
lb
*
lb
. Refer to
values
array description in BSR Format for more details.
The non-zero elements of the given row of the matrix must be stored in the same order as they appear in the row (from left to right).
No diagonal element can be omitted from a sparse storage if the solver is called with the non-unit indicator.
ia
Array of length
(
m
+ 1)
, containing indices of block in the array
a
, such that
ia
[
I
] -
ia
[0]
is the index in the array
a
of the first non-zero element from the row
I
. The value of the last element
ia
[
m
] -
ia
[0]
is equal to the number of non-zero blocks. Refer to
rowIndex
array description in BSR Format for more details.
ja
Array containing the column indices
plus one
for each non-zero block in the matrix
A
.
Its length is equal to the number of non-zero blocks of the matrix
A
. Refer to
columns
array description in BSR Format for more details.
x
Array, size
(
m
*
lb
)
.
On entry, the array
x
must contain the vector
x
.
Output Parameters
y
Array, size at least
(
m
*
lb
)
.
On exit, the array
y
must contain the vector
y
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804