Developer Reference

Contents

Graph Routines

Intel® Math Kernel Library (Intel® MKL)
provides a set of routines to perform various operations on graphs as represented in the language of linear algebra. The functionality is currently added in a preview mode. In this preview mode, the library provides only partial support for some of the documented functionality. For instance,
mkl_graph_mxm
and
mkl_graph_mxv
support different subsets of the full list of semirings. Supported configurations are documented for each routine, and routines will return
MKL_GRAPH_STATUS_NOT_SUPPORTED
when the input configuration is not supported. As a best practice, always check for successful return status (
MKL_GRAPH_STATUS_SUCCESS
) from all calls to the MKL graph routines. More functionality will be added in future releases. The API is based on the GraphBLAS C API specification, but is less general and has a more limited scope. Comments, questions and suggestions are encouraged and should be submitted to the
Intel® Math Kernel Library (Intel® MKL)
.
The terms and concepts required to understand the use of the
Intel® MKL
graph routines are discussed in Appendix F: Graph Basics. If you are familiar with GraphBLAS terminology and sparse matrix storage schemes, you can skip these sections and go directly to the interface descriptions.
Refer to the description of
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804