Developer Reference

Contents

?tfttp

Copies a triangular matrix from the rectangular full packed format (TF) to the standard packed format (TP) .

Syntax

lapack_int
LAPACKE_stfttp
(
int
matrix_layout
,
char
transr
,
char
uplo
,
lapack_int
n
,
const
float
*
arf
,
float
*
ap
);
lapack_int
LAPACKE_dtfttp
(
int
matrix_layout
,
char
transr
,
char
uplo
,
lapack_int
n
,
const
double
*
arf
,
double
*
ap
);
lapack_int
LAPACKE_ctfttp
(
int
matrix_layout
,
char
transr
,
char
uplo
,
lapack_int
n
,
const
lapack_complex_float
*
arf
,
lapack_complex_float
*
ap
);
lapack_int
LAPACKE_ztfttp
(
int
matrix_layout
,
char
transr
,
char
uplo
,
lapack_int
n
,
const
lapack_complex_double
*
arf
,
lapack_complex_double
*
ap
);
Include Files
  • mkl.h
Description
The routine copies a triangular matrix
A
from the Rectangular Full Packed (RFP) format to the standard packed format. For the description of the RFP format, see Matrix Storage Schemes .
Input Parameters
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
transr
= 'N':
arf
is in the Normal format,
= 'T':
arf
is in the Transpose format (for
stfttp
and
dtfttp
),
= 'C':
arf
is in the Conjugate-transpose format (for
ctfttp
and
ztfttp
).
uplo
Specifies whether
A
is upper or lower triangular:
= 'U': A is upper triangular,
= 'L': A is lower triangular.
n
The order of the matrix
A
.
n
0
.
arf
Array, size at least
max
(1,
n
*(
n
+1)/2).
On entry, the upper or lower triangular matrix
A
stored in the RFP format.
Output Parameters
ap
Array, size at least
max
(1,
n
*(
n
+1)/2).
On exit, the upper or lower triangular matrix
A
, packed columnwise in a linear array.
Return Values
This function returns a value
info
.
If
info
= 0
, the execution is successful.
If
info
< 0
, the
i
-th parameter had an illegal value.
If
info
= -1011
, memory allocation error occurred.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804