Contents

# ?sytrf_aa

Computes the factorization of a symmetric matrix using Aasen's algorithm.
Description
?sytrf_aa
computes the factorization of a symmetric matrix A using Aasen's algorithm. The form of the factorization is A = U*T*U
T
or A = L*T*L
T
where U (or L) is a product of permutation and unit upper (lower) triangular matrices, and T is a complex symmetric tridiagonal matrix.
This is the blocked version of the algorithm, calling Level 3 BLAS.
Input Parameters
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
uplo
• =
'U'
: The upper triangle of A is stored.
• =
'L'
: The lower triangle of A is stored.
n
The order of the matrix A.
n
≥ 0.
A
Array of size max(1,
lda
*
n
). The array
A
contains either the upper or the lower triangular part of the matrix A (see
uplo
).
lda
The leading dimension of the array
A
.
Output Parameters
A
On exit, the tridiagonal matrix is stored in the diagonals and the subdiagonals of A just below (or above) the diagonals, and L is stored below (or above) the subdiagonals, when
uplo
is
'L'
(or
'U'
).
ipiv
Array of size
n
.
On exit, it contains the details of the interchanges; that is, the row and column
k
of A were interchanged with the row and column
ipiv
(
k
)
.
Return Values
This function returns a value
info
.
= 0: Successful exit.
< 0: If
info
=
-i
, the
i
th
> 0: If
info
=
i
, D(
i
,
i
) is exactly zero. The factorization has been completed, but the block diagonal matrix D is exactly singular, and division by zero will occur if it is used to solve a system of equations.

#### Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804