Developer Reference

Contents

?spsv

Computes the solution to the system of linear equations with a real or complex symmetric coefficient matrix A stored in packed format, and multiple right-hand sides.

Syntax

lapack_int
LAPACKE_sspsv
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
lapack_int
nrhs
,
float
*
ap
,
lapack_int
*
ipiv
,
float
*
b
,
lapack_int
ldb
);
lapack_int
LAPACKE_dspsv
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
lapack_int
nrhs
,
double
*
ap
,
lapack_int
*
ipiv
,
double
*
b
,
lapack_int
ldb
);
lapack_int
LAPACKE_cspsv
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
lapack_int
nrhs
,
lapack_complex_float
*
ap
,
lapack_int
*
ipiv
,
lapack_complex_float
*
b
,
lapack_int
ldb
);
lapack_int
LAPACKE_zspsv
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
lapack_int
nrhs
,
lapack_complex_double
*
ap
,
lapack_int
*
ipiv
,
lapack_complex_double
*
b
,
lapack_int
ldb
);
Include Files
  • mkl.h
Description
The routine solves for
X
the real or complex system of linear equations
A*X
=
B
, where
A
is an
n
-by-
n
symmetric matrix stored in packed format, the columns of matrix
B
are individual right-hand sides, and the columns of
X
are the corresponding solutions.
The diagonal pivoting method is used to factor
A
as
A
=
U*D*U
T
or
A
=
L*D*L
T
, where
U
(or
L
) is a product of permutation and unit upper (lower) triangular matrices, and
D
is symmetric and block diagonal with 1-by-1 and 2-by-2 diagonal blocks.
The factored form of
A
is then used to solve the system of equations
A*X
=
B
.
Input Parameters
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
uplo
Must be
'U'
or
'L'
.
Indicates whether the upper or lower triangular part of
A
is stored:
If
uplo
=
'U'
, the upper triangle of
A
is stored.
If
uplo
=
'L'
, the lower triangle of
A
is stored.
n
The order of matrix
A
;
n
0.
nrhs
The number of right-hand sides, the number of columns in
B
;
nrhs
0
.
ap
,
b
Arrays:
ap
(size max(1,
n
*(
n
+1)/2)
,
b
of size max(1,
ldb
*
nrhs
) for column major layout and max(1,
ldb
*
n
) for row major layout
.
The array
ap
contains the factor
U
or
L
, as specified by
uplo
, in packed storage (see Matrix Storage Schemes ).
The array
b
contains the matrix
B
whose columns are the right-hand sides for the systems of equations.
ldb
The leading dimension of
b
;
ldb
max(1,
n
) for column major layout and
ldb
nrhs
for row major layout
.
Output Parameters
ap
The block-diagonal matrix
D
and the multipliers used to obtain the factor
U
(or
L
) from the factorization of
A
as computed by
?sptrf
, stored as a packed triangular matrix in the same storage format as
A
.
b
If
info
= 0,
b
is overwritten by the solution matrix
X
.
ipiv
Array, size at least
max(1,
n
)
. Contains details of the interchanges and the block structure of
D
, as determined by
?sptrf
.
If
ipiv
[
i
-1] =
k
> 0
, then
d
i
i
is a 1-by-1 block, and the
i
-th row and column of
A
was interchanged with the
k
-th row and column.
If
uplo
=
'U'
and
ipiv
[
i
]=
ipiv
[
i
-1] = -
m
< 0, then
D
has a 2-by-2 block in rows/columns
i
and
i
+1, and
i
-th row and column of
A
was interchanged with the
m
-th row and column.
If
uplo
=
'L'
and
ipiv
[
i
-1] =
ipiv
[
i
] = -
m
< 0, then
D
has a 2-by-2 block in rows/columns
i
and
i
+1, and (
i
+1)-th row and column of
A
was interchanged with the
m
-th row and column.
Return Values
This function returns a value
info
.
If
info
= 0
, the execution is successful.
If
info
=
-i
, parameter
i
had an illegal value.
If
info
=
i
,
d
i
i
is 0. The factorization has been completed, but
D
is exactly singular, so the solution could not be computed.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804