Developer Reference

Contents

?laghe

Generates a complex Hermitian matrix .

Syntax

lapack_int
LAPACKE_claghe
(
int
matrix_layout
,
lapack_int
n
,
lapack_int
k
,
const
float
*
d
,
lapack_complex_float
*
a
,
lapack_int
lda
,
lapack_int
*
iseed
);
lapack_int
LAPACKE_zlaghe
(
int
matrix_layout
,
lapack_int
n
,
lapack_int
k
,
const
double
*
d
,
lapack_complex_double
*
a
,
lapack_int
lda
,
lapack_int
*
iseed
);
Include Files
  • mkl.h
Description
The routine generates a complex Hermitian matrix
A
, by pre- and post- multiplying a real diagonal matrix
D
with random unitary matrix:
A
:=
U
*
D
*
U
H
The semi-bandwidth may then be reduced to
k
by additional unitary transformations.
Input Parameters
A
<datatype>
placeholder, if present, is used for the C interface data types in the C interface section above. See C Interface Conventions for the C interface principal conventions and type definitions.
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
n
The order of the matrix
A
(
n
0
).
k
The number of nonzero subdiagonals within the band of
A
(
0
k
n
-1)
.
d
The array
d
with the dimension of (
n
) contains the diagonal elements of the diagonal matrix
D
.
lda
The leading dimension of the array
a
(
lda
n
).
iseed
The array
iseed
with the dimension of 4 contains the seed of the random number generator. The elements must be between 0 and 4095 and
iseed
[3]
must be odd.
Output Parameters
a
The array
a
of size
at least max (1,
lda
*
n
)
contains the generated
n
-by-
n
Hermitian matrix
D
.
iseed
The array
iseed
contains the updated seed on exit.
Return Values
This function returns a value
info
.
If
info
= 0
, the execution is successful.
If
info
< 0
, the
i
-th parameter had an illegal value.
If
info
= -1011
, memory allocation error occurred.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804