Developer Reference

Contents

p?getf2

Computes an LU factorization of a general matrix, using partial pivoting with row interchanges (local blocked algorithm).

Syntax

void
psgetf2
(
MKL_INT
*m
,
MKL_INT
*n
,
float
*a
,
MKL_INT
*ia
,
MKL_INT
*ja
,
MKL_INT
*desca
,
MKL_INT
*ipiv
,
MKL_INT
*info
);
void
pdgetf2
(
MKL_INT
*m
,
MKL_INT
*n
,
double
*a
,
MKL_INT
*ia
,
MKL_INT
*ja
,
MKL_INT
*desca
,
MKL_INT
*ipiv
,
MKL_INT
*info
);
void
pcgetf2
(
MKL_INT
*m
,
MKL_INT
*n
,
MKL_Complex8
*a
,
MKL_INT
*ia
,
MKL_INT
*ja
,
MKL_INT
*desca
,
MKL_INT
*ipiv
,
MKL_INT
*info
);
void
pzgetf2
(
MKL_INT
*m
,
MKL_INT
*n
,
MKL_Complex16
*a
,
MKL_INT
*ia
,
MKL_INT
*ja
,
MKL_INT
*desca
,
MKL_INT
*ipiv
,
MKL_INT
*info
);
Include Files
  • mkl_scalapack.h
Description
The
p?getf2
function
computes an
LU
factorization of a general
m
-by-
n
distributed matrix sub(
A
) =
A
(
ia
:
ia
+
m
-1
,
ja
:
ja
+
n
-1)
using partial pivoting with row interchanges.
The factorization has the form
sub(
A
) =
P
*
L
*
U
, where
P
is a permutation matrix,
L
is lower triangular with unit diagonal elements (lower trapezoidal if
m
>
n
), and
U
is upper triangular (upper trapezoidal if
m
<
n
). This is the right-looking Parallel Level 2 BLAS version of the algorithm.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.
Input Parameters
m
(global)
The number of rows in the distributed matrix sub(
A
).
(
m
≥0)
.
n
(global) The number of columns in the distributed matrix sub(
A
).
(
nb_a
-
mod
(
ja
-1,
nb_a
)
n
0)
.
a
(local).
Pointer into the local memory to an array of size
lld_a
*
LOC
c
(
ja
+
n
-1)
.
On entry, this array contains the local pieces of the
m
-by-
n
distributed matrix sub(
A
).
ia
,
ja
(global) The row and column indices in the global matrix
A
indicating the first row and the first column of the matrix sub(
A
), respectively.
desca
(global and local) array of size
dlen_
. The array descriptor for the distributed matrix
A
.
Output Parameters
ipiv
(local)
Array of size
(
LOCr
(
m_a
) +
mb_a
)
. This array contains the pivoting information.
ipiv
[
i
]
-
>
The global row that local row
(
i
+1)
was swapped with
,
i
= 0, 1, ... ,
LOCr
(
m_a
) +
mb_a
- 1
. This array is tied to the distributed matrix
A
.
info
(local).
If
info
= 0
: successful exit.
If
info
< 0:
  • if the
    i
    -th argument is an array and the
    j
    -th entry
    , indexed
    j
    -1,
    had an illegal value, then
    info
    = -(
    i
    *100+
    j
    )
    ,
  • if the
    i
    -th argument is a scalar and had an illegal value, then
    info
    =
    - i
    .
If
info
>
0
: If
info
=
k
, the matrix element
U
(
ia
+
k
-1
,
ja
+
k
-1)
is exactly zero. The factorization has been completed, but the factor
U
is exactly singular, and division by zero will occur if it is used to solve a system of equations.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804