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Conditional Numerical Reproducibility Control

The CNR mode of
Intel® MKL
ensures bitwise reproducible results from run to run of
Intel® MKL
functions on a fixed number of threads for a specific Intel instruction set architecture (ISA) under the following conditions:
  • Calls to
    Intel® MKL
    occur in a single executable
  • The number of computational threads used by the library does not change in the run
Intel® MKL
offers both functions and environment variables to support conditional numerical reproducibility. See the
Intel® MKL
Developer Guide
for more information on bitwise reproducible results of computations and for details about the environment variables.
The support functions enable you to configure the CNR mode and also provide information on the current and optimal CNR branch on your system. Usage Examples for CNR Support Functions illustrate usage of these functions.
Call the functions that define the behavior of CNR before any of the math library functions that they control.
Intel® MKL
provides named constants for use as input and output parameters of the functions instead of integer values. See Named Constants for CNR Control for a list of the named constants.
Although you can configure the CNR mode using either the support functions or the environment variables, the functions offer more flexible configuration and control than the environment variables. Settings specified by the functions take precedence over the settings specified by the environment variables.
Use
Intel® MKL
in the CNR mode only in case a need for bitwise reproducible results is critical. Otherwise, run
Intel® MKL
as usual to avoid performance degradation.
While you can supply unaligned input and output data to
Intel® MKL
functions running in the CNR mode, use of aligned data is recommended. Refer to Reproducibility Conditions for more details.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804