Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

?swap

Swaps a vector with another vector.

Syntax

call sswap
(
n
,
x
,
incx
,
y
,
incy
)
call dswap
(
n
,
x
,
incx
,
y
,
incy
)
call cswap
(
n
,
x
,
incx
,
y
,
incy
)
call zswap
(
n
,
x
,
incx
,
y
,
incy
)
call swap
(
x
,
y
)
Include Files
  • mkl.fi
    ,
    blas.f90
Description
Given two vectors
x
and
y
, the
?swap
routines return vectors
y
and
x
swapped, each replacing the other.
Input Parameters
n
INTEGER
.
Specifies the number of elements in vectors
x
and
y
.
x
REAL
for
sswap
DOUBLE PRECISION
for
dswap
COMPLEX
for
cswap
DOUBLE COMPLEX
for
zswap
Array, size at least
(1 + (
n
-1)*abs(
incx
))
.
incx
INTEGER
.
Specifies the increment for the elements of
x
.
y
REAL
for
sswap
DOUBLE PRECISION
for
dswap
COMPLEX
for
cswap
DOUBLE COMPLEX
for
zswap
Array, size at least
(1 + (
n
-1)*abs(
incy
))
.
incy
INTEGER
.
Specifies the increment for the elements of
y
.
Output Parameters
x
Contains the resultant vector
x
, that is, the input vector
y
.
y
Contains the resultant vector
y
, that is, the input vector
x
.
BLAS 95 Interface Notes
Routines in Fortran 95 interface have fewer arguments in the calling sequence than their FORTRAN 77 counterparts. For general conventions applied to skip redundant or reconstructible arguments, see BLAS 95 Interface Conventions.
Specific details for the routine
swap
interface are the following:
x
Holds the vector with the number of elements
n
.
y
Holds the vector with the number of elements
n
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804