Developer Reference

  • 098
  • 03/30/2020
  • Public Content
Contents

?axpyi

Adds a scalar multiple of compressed sparse vector to a full-storage vector.

Syntax

call saxpyi
(
nz
,
a
,
x
,
indx
,
y
)
call daxpyi
(
nz
,
a
,
x
,
indx
,
y
)
call caxpyi
(
nz
,
a
,
x
,
indx
,
y
)
call zaxpyi
(
nz
,
a
,
x
,
indx
,
y
)
call axpyi
(
x
,
indx
,
y
[
,
a
]
)
Include Files
  • mkl.fi
    ,
    blas.f90
Description
The
?axpyi
routines perform a vector-vector operation defined as
y
:=
a
*
x
+
y
where:
a
is a scalar,
x
is a sparse vector stored in compressed form,
y
is a vector in full storage form.
The
?axpyi
routines reference or modify only the elements of
y
whose indices are listed in the array
indx
.
The values in
indx
must be distinct.
Input Parameters
nz
INTEGER
.
The number of elements in
x
and
indx
.
a
REAL
for
saxpyi
DOUBLE PRECISION
for
daxpyi
COMPLEX
for
caxpyi
DOUBLE COMPLEX
for
zaxpyi
Specifies the scalar
a
.
x
REAL
for
saxpyi
DOUBLE PRECISION
for
daxpyi
COMPLEX
for
caxpyi
DOUBLE COMPLEX
for
zaxpyi
Array, size at least
nz
.
indx
INTEGER
.
Specifies the indices for the elements of
x
.
Array, size at least
nz
.
y
REAL
for
saxpyi
DOUBLE PRECISION
for
daxpyi
COMPLEX
for
caxpyi
DOUBLE COMPLEX
for
zaxpyi
Array, size at least
max(
indx
(i))
.
Output Parameters
y
Contains the updated vector
y
.
BLAS 95 Interface Notes
Routines in Fortran 95 interface have fewer arguments in the calling sequence than their FORTRAN 77 counterparts. For general conventions applied to skip redundant or reconstructible arguments, see BLAS 95 Interface Conventions.
Specific details for the routine
axpyi
interface are the following:
x
Holds the vector with the number of elements
nz
.
indx
Holds the vector with the number of elements
nz
.
y
Holds the vector with the number of elements
nz
.
a
The default value is 1.
1

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804