Developer Reference

  • 098
  • 03/30/2020
  • Public Content
Contents

?gthr

Gathers a full-storage sparse vector's elements into compressed form.

Syntax

call sgthr
(
nz
,
y
,
x
,
indx
)
call dgthr
(
nz
,
y
,
x
,
indx
)
call cgthr
(
nz
,
y
,
x
,
indx
)
call zgthr
(
nz
,
y
,
x
,
indx
)
res
=
gthr
(
x
,
indx
,
y
)
Include Files
  • mkl.fi
    ,
    blas.f90
Description
The
?gthr
routines gather the specified elements of a full-storage sparse vector
y
into compressed form(
nz
,
x
,
indx
). The routines reference only the elements of
y
whose indices are listed in the array
indx
:
x(
i
) =
y
(
indx
(
i
))
, for
i
=1,2,... ,
nz
.
Input Parameters
nz
INTEGER
.
The number of elements of
y
to be gathered.
indx
INTEGER
.
Specifies indices of elements to be gathered.
Array, size at least
nz
.
y
REAL
for
sgthr
DOUBLE PRECISION
for
dgthr
COMPLEX
for
cgthr
DOUBLE COMPLEX
for
zgthr
Array, size at least max(
indx(i)
).
Output Parameters
x
REAL
for
sgthr
DOUBLE PRECISION
for
dgthr
COMPLEX
for
cgthr
DOUBLE COMPLEX
for
zgthr
Array, size at least
nz
.
Contains the vector converted to the compressed form.
BLAS 95 Interface Notes
Routines in Fortran 95 interface have fewer arguments in the calling sequence than their FORTRAN 77 counterparts. For general conventions applied to skip redundant or reconstructible arguments, see BLAS 95 Interface Conventions.
Specific details for the routine
gthr
interface are the following:
x
Holds the vector with the number of elements
nz
.
indx
Holds the vector with the number of elements
nz
.
y
Holds the vector with the number of elements
nz
.
1

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804