Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

?la_herpvgrw

Computes the reciprocal pivot growth factor
norm(A)/norm(U)
for a Hermitian indefinite matrix.

Syntax

call cla_herpvgrw
(
uplo
,
n
,
info
,
a
,
lda
,
af
,
ldaf,
ipiv
,
work
)
call zla_herpvgrw
(
uplo
,
n
,
info
,
a
,
lda
,
af
,
ldaf,
ipiv
,
work
)
Include Files
  • mkl.fi
Description
The
?la_herpvgrw
routine computes the reciprocal pivot growth factor
norm(
A)
/norm(
U
)
. The max absolute element norm is used. If this is much less than 1, the stability of the
LU
factorization of the equilibrated matrix
A
could be poor. This also means that the solution
X
, estimated condition numbers, and error bounds could be unreliable.
Input Parameters
uplo
CHARACTER*1
. Must be
'U'
or
'L'
.
Specifies the triangle of A to store:
If
uplo
=
'U'
, the upper triangle of
A
is stored,
If
uplo
=
'L'
, the lower triangle of
A
is stored.
n
INTEGER
. The number of linear equations, the order of the matrix
A
;
n
0.
info
INTEGER
. The value of INFO returned from
?hetrf
, that is, the pivot in column
info
is exactly 0.
a
,
af
COMPLEX
for
cla_herpvgrw
DOUBLE COMPLEX
for
zla_herpvgrw
.
Arrays:
a
(
lda
,*)
,
af
(
ldaf
,*)
.
a
contains the
n
-by-
n
matrix
A
. The second dimension of
a
must be at least
max(1,
n
)
.
af
contains the block diagonal matrix D and the multipliers used to obtain the factor U or L as computed by
?hetrf
. The second dimension of
af
must be at least
max(1,
n
)
.
lda
INTEGER
. The leading dimension of array
a
;
lda
max(1,
n
)
.
ldaf
INTEGER
. The leading dimension of array
af
;
ldaf
max(1,
n
)
.
ipiv
INTEGER
.
Array,
DIMENSION
n
. Details of the interchanges and the block structure of D as determined by
?hetrf
.
work
REAL
for
cla_herpvgrw
DOUBLE PRECISION
for
zla_herpvgrw
.
Array,
DIMENSION
2*
n.
Workspace.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804