Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

?lasq1

Computes the singular values of a real square bidiagonal matrix. Used by
?bdsqr
.

Syntax

call slasq1
(
n
,
d
,
e
,
work
,
info
)
call dlasq1
(
n
,
d
,
e
,
work
,
info
)
Include Files
  • mkl.fi
Description
The routine
?lasq1
computes the singular values of a real
n
-by-
n
bidiagonal matrix
Z
with diagonal
d
and off-diagonal
e
. The singular values are computed to high relative accuracy, in the absence of denormalization, underflow and overflow.
Input Parameters
n
INTEGER
.The number of rows and columns in the matrix.
n
0
.
d
REAL
for
slasq1
DOUBLE PRECISION
for
dlasq1
.
Array,
DIMENSION
(
n
).
On entry,
d
contains the diagonal elements of the bidiagonal matrix whose
SVD
is desired.
e
REAL
for
slasq1
DOUBLE PRECISION
for
dlasq1
.
Array,
DIMENSION
(
n
).
On entry, elements
e
(1:
n
-1)
contain the off-diagonal elements of the bidiagonal matrix whose
SVD
is desired.
work
REAL
for
slasq1
DOUBLE PRECISION
for
dlasq1
.
Workspace array,
DIMENSION
(4
n
)
.
Output Parameters
d
On normal exit,
d
contains the singular values in decreasing order.
e
On exit,
e
is overwritten.
info
INTEGER
.
= 0: successful exit;
< 0: if
info
= -
i
, the
i
-th argument had an illegal value;
> 0: the algorithm failed:
= 1, a split was marked by a positive value in
e
;
= 2, current block of
Z
not diagonalized after 100
n
iterations (in inner while loop) - on exit the current contents of
d
and
e
represent a matrix with the same singular values as the matrix with which
?lasq1
was originally called, and which the calling subroutine could use to finish the computation, or even feed back into
?lasq1
;
= 3, termination criterion of outer while loop not met (program created more than
n
unreduced blocks.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804