Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

?lasrt2

Sorts numbers in increasing or decreasing order.

Syntax

call slasrt2
(
id
,
n
,
d
,
key
,
info
)
call dlasrt2
(
id
,
n
,
d
,
key
,
info
)
Description
The
?lasrt2
routine
is modified LAPACK
routine
?lasrt
, which sorts the numbers in
d
in increasing order (if
id
=
'I'
) or in decreasing order (if
id
=
'D'
). It uses Quick Sort, reverting to Insertion Sort on arrays of size
20. The size of
STACK
limits
n
to about 2
32
.
Input Parameters
id
CHARACTER*1
.
=
'I'
: sort
d
in increasing order;
=
'D'
: sort
d
in decreasing order.
n
INTEGER
.
The length of the array
d
.
d
REAL
for
slasrt2
DOUBLE PRECISION
for
dlasrt2
.
Array of size
n
.
On entry, the array to be sorted.
key
INTEGER
.
Array of size
n
.
On entry,
key
contains a key to each of the entries in
d
()
.
Typically,
key
(
i
) =
i
for all
i
.
Output Parameters
d
On exit,
d
has been sorted into increasing order
(
d
(1)
...
d
(
n
) )
or into decreasing order
(
d
(1)
...
d
(
n
) )
,
depending on
id
.
info
INTEGER
.
= 0
: successful exit
< 0
: if
info
= -i
, the
i
-th argument had an illegal value.
key
On exit,
key
is permuted in exactly the same manner as
d
was permuted from input to output. Therefore, if
key
(
i
) =
i
for all
i
on input,
d
(
i
) on output equals
d
(
key
(
i
)) on input
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804