Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

p?pbtrsv

Solves a single triangular linear system via frontsolve or backsolve where the triangular matrix is a factor of a banded matrix computed by
p?pbtrf
.

Syntax

call pspbtrsv
(
uplo
,
trans
,
n,
bw
,
nrhs
,
a
,
ja
,
desca
,
b
,
ib
,
descb
,
af
,
laf
,
work
,
lwork
,
info
)
call pdpbtrsv
(
uplo
,
trans
,
n
,
bw
,
nrhs
,
a
,
ja
,
desca
,
b
,
ib
,
descb
,
af
,
laf
,
work
,
lwork
,
info
)
call pcpbtrsv
(
uplo
,
trans
,
n
,
bw
,
nrhs
,
a
,
ja
,
desca
,
b
,
ib
,
descb
,
af
,
laf
,
work
,
lwork
,
info
)
call pzpbtrsv
(
uplo
,
trans
,
n
,
bw
,
nrhs
,
a
,
ja
,
desca
,
b
,
ib
,
descb
,
af
,
laf
,
work
,
lwork
,
info
)
Description
The
p?pbtrsv
routine
solves a banded triangular system of linear equations
A
(1:
n
,
ja
:
ja
+
n
-1)*
X
=
B
(
jb
:
jb+n
-1, 1:
nrhs
)
or
A
(1:
n
,
ja
:
ja
+
n
-1)
T
*
X
=
B
(
jb
:
jb+n
-1, 1:
nrhs
)
for real flavors,
A
(1:
n
,
ja
:
ja
+
n
-1)
H
*
X
=
B
(
jb
:
jb+n
-1, 1:
nrhs
)
for complex flavors,
where
A
(1:
n
,
ja
:
ja
+
n
-1)
is a banded triangular matrix factor produced by the Cholesky factorization code
p?pbtrf
and is stored in
A
(1:
n
,
ja
:
ja
+
n
-1)
and
af
. The matrix stored in
A
(1:
n
,
ja
:
ja
+
n
-1)
is either upper or lower triangular according to
uplo
.
The routine
p?pbtrf
must be called first.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.
Input Parameters
uplo