Developer Reference

  • 2020.2
  • 07/15/2020
  • Public Content
Contents

mkl_pardiso_pivot

Replaces routine which handles
Intel® MKL
PARDISO pivots with user-defined routine.

Syntax

call mkl_pardiso_pivot
(
ai
,
bi
,
eps
)
Include Files
  • mkl.fi
    ,
    mkl_pardiso.f90
Description
The
mkl_pardiso_pivot
routine allows you to handle diagonal elements which arise during numerical factorization that are zero or near zero. By default,
Intel® MKL
PARDISO determines that a diagonal element
bi
is a pivot if
bi
<
eps
, and if so, replaces it with
eps
. But you can provide your own routine to modify the resulting factorized matrix in case there are small elements on the diagonal during the factorization step.
To use this routine, you must set
iparm
(56)
to 1 before the main
pardiso
loop.
This routine is only available for in-core
Intel® MKL
PARDISO.
Input Parameters
ai
DOUBLE PRECISION
- for real types of matrices (
mtype
=2, -2, 4, and 6) and for double precision
Intel® MKL
PARDISO (
iparm
(28)
=0)
Diagonal element of initial matrix corresponding to pivot element.
bi
DOUBLE PRECISION
- for real types of matrices (
mtype
=2, -2, 4, and 6) and for double precision
Intel® MKL
PARDISO (
iparm
(28)
=0)
Diagonal element of factorized matrix that could be chosen as a pivot element.
eps
DOUBLE PRECISION
Scalar to compare with diagonal of factorized matrix. On input equal to parameter described by
iparm
(10)
.
Output Parameters
bi
In case element is chosen as a pivot, value with which to replace the pivot.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804