Named Constants for CNR Control
Use the conditional numerical reproducibility (CNR) functionality in
to obtain reproducible results from MKL routines. When enabling CNR, you choose a specific code branch of
that corresponds to the instruction set architecture (ISA) that you target. Use these named constants to specify the code branch and other CNR options.
Disable CNR mode
CNR mode is disabled
Choose branch automatically. CNR mode uses the standard ISA-based dispatching model while ensuring fixed cache sizes, deterministic reductions, and static scheduling
Intel® Streaming SIMD Extensions 2 (Intel® SSE2) without rcpps/rsqrtps instructions
DEPRECATED.Intel® Streaming SIMD Extensions 3 (Intel® SSE3)
. This setting is kept for backward compatibility and is equivalent to
Supplemental Streaming SIMD Extensions 3 (SSSE3)
Intel® Streaming SIMD Extensions 4-1 (SSE4-1)
Intel® Streaming SIMD Extensions 4-2 (SSE4-2)
Intel® Advanced Vector Extensions (Intel® AVX)
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) on Intel® Xeon Phi™ processors
Intel AVX-512 on Intel® Xeon® processors
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) for Intel® Many Integrated Core Architecture (Intel® MIC Architecture) with support of AVX512_4FMAPS and AVX512_4VNNIW instruction groups enabled processors
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) with support of Vector Neural Network Instructions enabled processors
When specifying the CNR branch with the named constants, be aware of the following:
- Settings other thanMKL_CBWR_AUTOorMKL_CBWR_COMPATIBLEare available only for Intel processors.
- Intel and Intel compatible CPUs have a few instructions, such as approximation instructions rcpps/rsqrtps, that may return different results. Setting the branch toMKL_CBWR_COMPATIBLEensures thatdoes not use these instructions and forces a single Intel SSE2-only code path to be executed.Intel® MKL
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.