Developer Guide

Contents

Configuring Parameters

The most significant parameters in
HPL.dat
are
P, Q, NB
, and
N
. Specify them as follows:
  • P
    and
    Q
    - the number of rows and columns in the process grid, respectively.
    P*Q
    must be the number of MPI processes that HPL is using.
    Choose
    P
    Q
    .
  • NB
    - the block size of the data distribution.
    The table below shows recommended values of
    NB
    for different Intel® processors:
    Processor
    NB
    Intel® Xeon® Processor X56*/E56*/E7-*/E7*/X7* (codenamed Nehalem or Westmere)
    256
    Intel Xeon Processor E26*/E26* v2 (codenamed Sandy Bridge or Ivy Bridge)
    256
    Intel Xeon Processor E26* v3/E26* v4 (codenamed Haswell or Broadwell)
    192
    Intel® Core™ i3/i5/i7-6* Processor (codenamed Skylake Client)
    192
    Intel® Xeon Phi™ Processor 72* (codenamed Knights Landing)
    336
    Intel Xeon Processor supporting Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions (codenamed Skylake Server)
    384
  • N
    - the problem size:
    Increasing
    N
    usually increases performance, but the size of
    N
    is bounded by memory. In general, you can compute the memory required to store the matrix (which does not count internal buffers) as 8*
    N
    *
    N
    /(
    P
    *
    Q
    ) bytes, where
    N
    is the problem size and
    P
    and
    Q
    are the process grids in
    HPL.dat
    . A general rule of thumb is to choose a problem size that fills 80% of memory.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804