Developer Guide

Contents

Environment Variables

The table below lists
Intel® MKL
environment variables to control runs of the Intel Distribution for LINPACK Benchmark.
Environment Variable
Description
Value
HPL_LARGEPAGE
Defines the memory mapping to be used for the Intel Xeon processor.
0 or 1:
  • 0 - normal memory mapping, default.
  • 1 - memory mapping with large pages (2 MB per page mapping). It may increase performance.
HPL_LOG
Controls the level of detail for the HPL output.
An integer ranging from 0 to 2:
  • 0 - no log is displayed.
  • 1 - only one root node displays a log, exactly the same as the
    ASYOUGO
    option provides.
  • 2 - the most detailed log is displayed. All
    P
    root nodes in the processor column that owns the current column block display a log.
HPL_HOST_CORE
,
HPL_HOST_NODE
Specifies cores or Non-Uniform Memory Access (NUMA) nodes to be used.
HPL_HOST_NODE
requires NUMA mode to be enabled. You can check whether it is enabled by the
numactl –-hardware
command.
The default behavior is auto-detection of the core or NUMA node.
A list of integers ranging from 0 to the largest number of a core or NUMA node in the cluster and separated as explained in example 3.
HPL_SWAPWIDTH
Specifies width for each swap operation.
16 or 24. The default is 24.
You can set Intel Distribution for LINPACK Benchmark environment variables using the
PMI_RANK
and
PMI_SIZE
environment variables of the Intel MPI library, and you can create a shell script to automate the process.

Examples of Environment Settings

#
Settings
Behavior of the Intel Distribution for LINPACK Benchmark
1
Nothing specified
All Intel Xeon processors in the cluster are used.
2
HPL_MIC_DEVICE
=0,2
HPL_HOST_CORE
=1-3,8-10
Intel Xeon processor cores 1,2,3,8,9, and 10 are used.
3
HPL_HOST_NODE
=1
Only Intel Xeon processor cores on NUMA node 1 are used.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804