• 2020
  • 04/01/2020
  • Public Content
Contents

Running the Software

To obtain results for the pre-determined sample problem sizes on a given system, type:
./
runme_xeon32
./
runme
_xeon
64
To run the software for other problem sizes, see the extended help included with the program. You can view extended help by running the program executable with the
-e
option:
./
x
linpack_
xeon32
-e
./
x
linpack_
xeon
64 -e
The pre-defined data input file
s
lininput_xeon32
,
lininput_xeon64
,
are
example
s
. Different systems have different
numbers of processors or
amounts of memory and therefore require new input files. The extended help can give insight into proper ways to change the sample input files.
Each input file requires the following minimum amount of memory:
lininput_xeon32      
      2 GB
lininput_xeon64      
     16 GB
If the system has less memory than the above sample data input requires, you may need to edit or create your own data input files, as explained in the extended help.
The Intel Optimized LINPACK Benchmark determines the optimal number of OpenMP threads to use. To run a different number, you can set the
OMP_NUM_THREADS
or
MKL_NUM_THREADS
environment variable inside a sample script. If you run the Intel Optimized LINPACK Benchmark without setting the number of threads, it defaults to the number of physical cores.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.
1

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804