Developer Guide

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MKL_DYNAMIC

The
MKL_DYNAMIC
environment variable enables
Intel® MKL
to dynamically change the number of threads.
The default value of
MKL_DYNAMIC
is
TRUE
, regardless of
OMP_DYNAMIC
, whose default value may be
FALSE
.
When
MKL_DYNAMIC
is
TRUE,
Intel® MKL
may use fewer OpenMP threads than the maximum number you specify.
For example,
MKL_DYNAMIC
set to
TRUE
enables optimal choice of the number of threads in the following cases:
  • If the requested number of threads exceeds the number of physical cores (perhaps because of using the Intel® Hyper-Threading Technology),
    Intel® MKL
    scales down the number of OpenMP threads to the number of physical cores.
  • If you are able to detect the presence of a message-passing interface (MPI), but cannot determine whether it has been called in a thread-safe mode,
    Intel® MKL
    runs one OpenMP thread.
When
MKL_DYNAMIC
is
FALSE
,
Intel® MKL
uses the suggested number of OpenMP threads whenever the underlying algorithms permit.For example, if you attempt to do a size one matrix-matrix multiply across eight threads, the library may instead choose to use only one thread because it is impractical to use eight threads in this event.
If
Intel® MKL
is called from an OpenMP parallel region in your program,
Intel® MKL
uses only one thread by default. If you want
Intel® MKL
to go parallel in such a call, link your program against an OpenMP threading RTL supported by
Intel® MKL
and set the environment variables:
  • OMP_NESTED
    to
    TRUE
  • OMP_DYNAMIC
    and
    MKL_DYNAMIC
    to
    FALSE
  • MKL_NUM_THREADS
    to some reasonable value
With these settings,
Intel® MKL
uses
MKL_NUM_THREADS
threads when it is called from the OpenMP parallel region in your program.
In general, set
MKL_DYNAMIC
to
FALSE
only under circumstances that
Intel® MKL
is unable to detect, for example, to use nested parallelism where the library is already called from a parallel section.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804